Field of Invention
The present invention relates to digital-to-analog conversion, including methods and circuits to improve the spur-free-dynamic range (SFDR) and to minimize spurs associated with even harmonic distortions at high frequencies of a high speed current steering digital-to-analog converter (DAC).
Discussion of the Background
Recent advances in wireless communication systems and the unprecedented surge in demand for high data rates have led to developments of DACs in the Giga-Herz (GHz) space to generate wideband radio-frequency (RF) signals from digital inputs. These applications typically have great demand on the digital-to-analog converter (DAC) linearity at high speed to increase the spur-free-dynamic range (SFDR). The high-frequency behavior of the DAC is typically dominated by dynamic distortions, although static linearity is necessary but not sufficient. Those skilled in the art know that among the various existing DAC architectures, current-steering DAC architecture is the primary choice for the high frequency wideband applications. In such current steering architectures, for high speed operation, the most-significant bits (MSBs) are typically implemented with the thermometer-code decoder, while the least-significant bits (LSBs) are implemented with the R-2R binary-weighted design 102, as shown in FIG. 1, in which the incoming binary signals are translated into drive signals for the current switch modules 104. The differential digital drive signals steer the current source in each current switch module 104 to one of the DAC differential outputs OUTP and OUTN. Typically, these currents are converted to voltages outside the DAC cell using resistors, or a combination of resistors and other passive components such as transformers or balun, as represented by the output network 106 in FIG. 1.
Despite their popularity at high-speeds, current-steering DACs are affected by dynamic non-linearity. These are the dynamic errors caused by device and interconnect parasitic, finite output impedance of current sources, code-dependent output impedance of DAC, glitches due to timing mismatch between digital driving signals and glitches caused by asymmetry in the settling behavior of current sources. These dynamic errors cause the SFDR performance of current steering DAC to fall rapidly with increases in signal frequency and clock rate.
Research has focused on circuit architectures and designs to minimize the 3rd order harmonic (3 HD) distortion and its related odd harmonic spurs caused by those dynamic errors. Research has not focused on minimizing even order harmonic related spurs, mainly because the even harmonics of the differential output configuration can be cancelled out in theory using balun or transformers in the output network to combine DAC outputs differentially. These methods had been quite effective at relatively low speed DAC with lower output frequencies.
However, as the DAC speed increases, even order harmonic spurs, particularly second order harmonic distortion (2 HD) spur, increase rapidly and will be folded back into the Nyquist band. As examples, for output frequencies located between ½ to ½ of the Nyquist band, the 2 HD spurs will show up in the second half of the Nyquist band. For higher output frequencies located in the second half of the Nyquist band, the 2 HD spurs will be folded back into the whole Nyquist band. All the spurs inside the Nyquist band cannot be filtered out for wideband applications. Since even order harmonic distortions co-exist in both complementary DAC outputs, ideally any method in the output network that can combine the two DAC outputs differentially will cancel out those even harmonic distortions, assuming the time delays for both outputs to arrive at the output network are the same. The same amount of mismatch of those two time delays will induce more phase difference at high frequencies and greatly reduce the effectiveness of even harmonic cancellation relying on the output network. More than that, the designs of prior art methods, such as balun, transformer or active linear amplifiers at high frequencies with wide bandwidth, create challenges for advanced applications. As an example, high frequency broadband balun are not popularly available. Moreover, the frequency response of a wideband balun typically is not flat and has low cut-off frequency. Both of these characteristics are not desirable for many high frequency wideband applications.
The problems of SFDR of high speed DAC limited by even harmonic distortions has been discussed in the literature. For example, one of the state-of-the-art high speed DACs was discussed by Van de Sande, F. et al, “A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz ft BiCMOS Process,” Solid-State Circuits, IEEE Journal of, vol. 47, no. 4, pp. 1003, 1012, April 2012 (“Sande”). The authors concluded from the measurement data that “For all FOUT, the SFDR is dominated by the (direct or folded) second or third harmonics: 2 FOUT, Fs−2 FOUT; 3 FOUT; Fs−3 FOUT”. As shown in FIG. 11 of Sande, the highest spur is the folded 2 HD Fs−2 FOUT. Even the measured data was taken with cascaded stages of balun to cancel the even harmonic spurs and other common mode noise.
A similar problem exists in commercial high speed DAC products. One example is shown in the Analog Devices, “AD9119/AD9129 11-/14-Bit, 5.7 GSPS, RF Digital-to-Analog Converter Data Sheet [Rev. A]”, September 2013 (the “AD9119/9129 data sheet”) in which the folded 2HD spur limits the SFDR to be 50 dB. See AD9119/9129 data sheet at FIG. 13. Even a balun was used at the outputs in the measurement to reduce even harmonic spurs.
There exists a need in the art for an improved high speed high frequency digital to analog converter.